During the manufacture of a semiconductor device such as a dynamic random access memory (DRAM), a programmable read-only memory (PROM) such as a flash electrically erasable PROM (EEPROM), a microprocessor, etc., various features are formed. For example, adjacent word lines each comprising a plurality of transistors are formed as access devices to electrical charges which may be stored on a plurality of storage capacitors and floating gates.
To reduce electrical interference between adjacent word lines, specifically interference between implanted regions within a semiconductor wafer over which the word lines will be formed, shallow trench isolation (STI) is provided early in semiconductor device processing. To form STI, a pad oxide layer and a silicon nitride layer are formed over the semiconductor wafer, a patterned photoresist layer is formed over the nitride, then the nitride, pad oxide, and semiconductor wafer are etched using the patterned photoresist layer as a mask to form a trench in the semiconductor wafer. The pad oxide reduces damage to the silicon wafer from formation of the nitride, and the nitride reduces oxidation of the wafer. Subsequently, the photoresist layer is removed and an oxide isolation is provided within the trench, typically using a high density plasma (HDP) to provide a blanket layer using a chemical vapor deposition (CVD) process. Subsequently, a mechanical planarization process, typically a chemical-mechanical polishing (CMP) process, is used to planarize the HDP oxide to the upper level of the nitride, which forms a damascene isolation within the trench. The nitride is then removed so that the upper surface of the HDP oxide is at a higher level than the surface of the semiconductor wafer. Various processing is performed to shape the HDP STI oxide, then word lines and other features required for proper device operation are formed during later wafer processing.
With decreasing feature sizes, various problems may occur with trench formation. For example, one such problem results from the relatively high height:width ratio (i.e. “aspect ratio”) of the trench to be filled. If the aspect ratio of the opening in the wafer exceeds about 4:1 for a trench which is about 50 nanometers (nm) wide, use of an HDP-CVD process will result in a void in the STI film. Voids in the isolation are to be avoided as they negatively affect the electrical operation of transistors adjacent the trench isolation. Typically, the top of the void should be separated from the gate oxide (for example for use with a dynamic random access memory device) or tunnel oxide (for example for use with a flash programmable read only memory device) by a minimum distance of at least about 500 to 800 angstroms (Å) to reduce or eliminate adverse electrical effects. Forming a deeper trench may not resolve the problem, as a larger void may form which extends to the same height as a void in the shallower trench.
For a given integrated circuit design, a void buried in the STI fill to a sufficient depth may be successfully achieved for most of the array structures. However, when statistically significant variations in critical dimensions are present, there are likely to be instances where the top of the buried void is too shallow for acceptable device performance.
A method for forming trench isolation which reduces or eliminates the problems described above, and an inventive structure resulting from the method, would be desirable.